1. Field of the Invention
The present invention relates to a low density parity check (LDPC) decoder and method for performing LDPC decoding, and in particular to an LDPC decoder and method using a layered belief propagation (LBP) algorithm.
2. Background to the Invention
Forward error correction (FEC) codes add redundancy to data packets to be transmitted over a transmission channel, such that errors introduced by noise in the transmission channel can be corrected by the receive circuitry.
LDPC codes are a type of forward error correction code, and are block based, encoding and decoding being performed based on a parity check matrix. The matrix is sparse, meaning that it comprises a low number of “1”s compared to “0”s, which is why such codes are referred to as low density codes.
At the transmitter side, blocks of N bits of data are transmitted, K bits of which correspond to information, and N-K bits of which correspond to redundancy added to the data. The parity check matrix comprises N-K rows and N columns.
At the receiver side, for decoding LDPC codes, log-likelihood ratio (LLR) values of the sets of symbols received by the receive circuitry are determined and provided as inputs to the LDPC decoder.
One LDPC decoding technique involves an iterative updating of the initial LLR values based on the parity check matrix H, performed row by row and then column by column. A faster technique has been proposed that uses an algorithm known as layered belief propagation (layered BP), according to which the H matrix is divided into layers, each layer comprising n rows of the matrix H. Furthermore, each layer is divided column-wise into sub-matrices, for example each comprising n by n values. Decoding is performed layer by layer based on the non-null sub-matrices in each layer, and the updated LLR values are directly used for processing the following layer, leading to a faster convergence of the algorithm.
LDPC decoders based on the layered BP algorithm generally use a memory to store the iteratively updated LLR values. Furthermore, to speed-up the throughput of the decoder, pipelined architectures have been proposed. However, due to the number of memory accesses required for retrieving LLR values, existing solutions tend to be far from optimal. There is thus a need for an improved LDPC decoder architecture.